1. Field of the Invention
The present invention relates to a semiconductor memory and, in particular, to a memory cell structure having improvements in resistance to soft error of a MOS static RAM.
2. Description of the Background Art
As the miniaturization of memory cells proceeds, the following soft error problem becomes noticeable. Specifically, the data stored in a storage node is inverted due to electrons generated from alpha rays released from a package and neutron beams from outer space. Particularly, as power supply voltage is lowered, malfunction becomes more significant. Attempts to reduce soft error are being pursued.
FIG. 37 is a circuit diagram illustrating a structure equivalent to a SRAM memory cell disclosed in, for example, Japanese Patent No. 2589949. As shown in FIG. 37, a memory cell 100 is made up of PMOS transistors PT1 and PT2, and NMOS transistors NT5 to NT8, NT11, NT12, NT21 and NT22.
The sources of the PMOS transistors PT1 and PT2 are both connected to a power supply voltage Vcc. The drain of the PMOS transistor PT1 is connected through a node 101 to the gate of the PMOS transistor PT2 and to the gates of the NMOS transistors NT21 and NT22. The drain of the PMOS transistor PT2 is connected through a node 111 to the gate of the PMOS transistor PT1 and to the gates of the NMOS transistors NT11 and NT12.
The sources of the NMOS transistors NT11 and NT12 are both grounded. The drain of the NMOS transistor NT11 is connected through the node 101 to the drain of the PMOS transistor PT1. The drain of the NMOS transistor NT12 is connected through the nodes 101 and 102 to the drain of the PMOS transistor PT1.
The sources of the NMOS transistors NT21 and NT22 are both grounded. The drain of the NMOS transistor NT21 is connected through the node 111 to the drain of the PMOS transistor PT2. The drain of the NMOS transistor NT22 is connected through the nodes 111 and 112 to the drain of the PMOS transistor PT2.
The NMOS transistor NT5 is interposed between a bit line BL50 and the node 101, and its gate is connected to a word line WL50. The NMOS transistor NT6 is interposed between a bit line BL60 and the node 101, and its gate is connected to a word line WL60. The NMOS transistor NT7 is interposed between a bit line BL51 and the node 111, and its gate is connected to the word line WL50. The NMOS transistor NT8 is interposed between a bit line BL61 and the node 111, and its gate is connected to the word line WL60.
In such a configuration, the word line WL50 or WL60 is brought into the active state and the NMOS transistors NT5 and NT6, or the NMOS transistors NT6 and NT8 are brought into the on state, thereby to provide access to the nodes 101 and 111, each being a storage node. This enables to obtain the data from the paired bit lines BL50 and BL51 or the paired bit lines BL60 and BL61.
In this configuration, a NMOS driver transistor that is usually made up of a single NMOS transistor is divided into two NMOS transistors (which is divided into the NMOS transistors NT11 and NT12, and NT21 and NT22).
In order to divide the storage node serving as the drain of the PMOS transistor PT1 (PT2) into the node 101 (111) and the node 102 (112), the NMOS transistor NT11 (NT21) and the NMOS transistor NT12 (NT22) are oppositely disposed so as to interpose therebetween N well region where the PMOS transistor PT1 is to be formed.
Therefore, the N well region prevents that a depletion region on the opposite side of the N well region is adversely affected by electrons or holes generated from energy particles colliding with one side of the N well region. This enables to lower incidence of soft error.
However, even with the foregoing SRAM memory cell, a reduction in soft error is insufficient. Further, there is the problem that the circuit configuration is complicated by using two driver transistors, although it can be generally configured by using one.